Integration of high voltage self-aligned MOS components
US6686233B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2001 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Jan 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a method for forming a high voltage NMOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, in an n-well CMOS process by adding solely two additional process steps to a conventional CMOS process: (i) a masking step, and (ii) an ion implantation step for forming a doped channel region for the high voltage MOS transistor in the substrate self-aligned to the edge of the high voltage MOS transistor gate region. The ion implantation is performed through the mask in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create the doped channel region partly underneath the gate region of the high voltage MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.