Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step
US6686244B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 21, 2002 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Apr 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
Abstract
A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and forming a voltage sustaining region on the substrate. The voltage sustaining region is formed in the following manner. First, an epitaxial layer is deposited on the substrate. The epitaxial layer has a first or a second conductivity type. Next, at least one terraced trench is formed in the epitaxial layer. The terraced trench has a trench bottom and a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls and bottom of the trench. A dopant of a conductivity type opposite to the conductivity type of the epitaxial layer is implanted through the barrier material lining the annular ledge and at the trench bottom and into adjacent portions of the epitaxial layer to respectively form at least one annular doped region and another doped region. The dopant is diffused in the annular doped region and the another doped region to cause the regions to overlap one another, whereby a continuous doped column is formed in the epitaxial layer. A filler material is deposited in …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.