Semiconductor structure and method for reducing charge damage
US6686254B2 · kind B2 · utility
7Cited by
12References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2001 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Jun 6, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor method for reducing charge damage during plasma etch processing is disclosed. Structures (22, 26, 28) for accumulating charge during plasma etch processing are provided on a semiconductor wafer (10), the structures (22, 26, 28) being electrically connected to device structures (30, 32).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.