Method of fabricating copper interconnects with very low-k inter-level insulator
US6686273B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2001 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Sep 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76801
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a low-k inter-level insulator structure is provided comprising the steps of: providing a first metal layer; depositing a sacrificial insulator layer overlying the first metal layer; producing a second metal layer; removing the sacrificial insulator layer; and depositing a low-k inter-level insulator, whereby low-k material replaces the sacrificial insulator. An intermediate insulator layer structure is also provided comprising a sacrificial insulator layer overlying a low-k insulator layer, such that the sacrificial insulator layer may be subjected to processes, including CMP, which may be incompatible with low-k insulator materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.