Wei Pan
73Patents
17h-index
30Co-inventors
84Inventor score
Filing activity: Jun 10, 1993 → Jan 23, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6849891B1 | RRAM memory cell electrodes | Physics | 174 | Expired |
| US6940113B2 | Trench isolated cross-point memory array | Physics | 115 | Expired |
| US7029924B2 | Buffered-layer memory cell | Physics | 94 | Expired |
| US6194310A | Method of forming amorphous conducting diffusion barriers | Electricity | 81 | Expired |
| US7193267B2 | Cross-point resistor memory array | Physics | 71 | Expired |
| US6972211B2 | Method of fabricating trench isolated cross-point memory array | Physics | 62 | Expired |
| US6905937B2 | Methods of fabricating a cross-point resistor memory array | Physics | 58 | Expired |
| US7205238B2 | Chemical mechanical polish of PCMO thin films for RRAM applications | Electricity | 56 | Expired |
| US7141481B2 | Method of fabricating nano-scale resistance cross-point memory array | Physics | 48 | Expired |
| US6555467B2 | Method of making air gaps copper interconnect | Electricity | 43 | Expired |
| US6548849B1 | Magnetic yoke structures in MRAM devices to reduce programming power consumption and a method to make the same | Physics | 32 | Expired |
| US5873977A | Dry etching of layer structure oxides | Electricity | 30 | Expired |
| US6939724B2 | Method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer | Physics | 26 | Expired |
| US7256429B2 | Memory cell with buffered-layer | Physics | 25 | Expired |
| US6156487A | Top surface imaging technique for top pole tip width control in magnetoresistive read/write head processing | Physics | 24 | Expired |
| US6887523B2 | Method for metal oxide thin film deposition via MOCVD | Physics | 22 | Expired |
| US6642138B2 | Process of making dual damascene structures using a sacrificial polymer | Electricity | 19 | Expired |
| US6927120B2 | Method for forming an asymmetric crystalline structure memory cell | Physics | 17 | Expired |
| US6746910B2 | Method of fabricating self-aligned cross-point memory array | Physics | 16 | Expired |
| US6686273B2 | Method of fabricating copper interconnects with very low-k inter-level insulator | Electricity | 16 | Expired |
| US6875651B2 | Dual-trench isolated crosspoint memory array and method for fabricating same | Physics | 14 | Expired |
| US6825058B2 | Methods of fabricating trench isolated cross-point memory array | Physics | 13 | Expired |
| US6841844B2 | Air gaps copper interconnect structure | Electricity | 13 | Expired |
| US6849564B2 | 1R1D R-RAM array with floating p-well | Physics | 13 | Expired |
| US5382320A | Reactive ion etching of lead zirconate titanate and ruthenium oxide thin films using CHClFCF.sub.3 or CHCl.sub.2 CF.sub.3 as an etch gas | Emerging Cross-Sectional Technologies | 13 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.