Semiconductor chip having both polycide and salicide gates and methods for making same
US6686276B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2002 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Aug 22, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A semiconductor process is provided that creates transistors having polycide gates in a first region of a semiconductor substrate and transistors having salicide gates in a second region of the semiconductor substrate. A polysilicon layer having a first portion in the first region and a second portion in the second region is formed over the semiconductor substrate. Then, a first dielectric layer is formed over the second portion of the polysilicon layer. Metal silicide is deposited over first portion of the polysilicon layer and the first dielectric layer. The metal silicide overlying the first dielectric layer is removed as is the first dielectric layer. The metal silicide and the polysilicon layer are etched to form polycide gates in the first region and polysilicon gates in the second region. A second dielectric layer is formed over the first region. Refractory metal is then deposited over the resulting structure and reacted. As a result, salicide is formed on the polysilicon gates of the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.