Method for forming a borderless contact of a semiconductor device
US6686286B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 25, 2002 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Jul 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76801
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a borderless contact of a semiconductor device includes forming a gate electrode on a field oxide of the semiconductor substrate, patterning a stacked structure of a buffer layer and an etching barrier layer on sidewalls of the gate electrode and on the field oxide, forming a silicide layer on the gate electrode and an active region exposed by the stacked structure, and forming the borderless contacts to reduce or prevent leakage current between the semiconductor device and the metal lines and degradation resulting from stresses inherent in the prior art nitride etching barrier layer by reducing abnormal oxidation associated with the buffer oxide layer under the etching barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.