Plasma etch method for forming uniform linewidth residue free patterned composite silicon containing dielectric layer/silicon stack layer
US6686292B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1998 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Dec 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a patterned composite stack layer within a microelectronics fabrication. There is first provided a substrate. There is then formed over the substrate a blanket silicon layer. There is then formed upon the blanket silicon layer a blanket silicon containing dielectric layer. There is then formed upon the blanket silicon containing dielectric layer a patterned photoresist layer. Finally, there is etched sequentially while employing the patterned photoresist layer as a photoresist etch mask the blanket silicon containing dielectric layer and the blanket silicon layer to form a patterned composite stack layer comprising a patterned silicon containing dielectric layer coextensive with a patterned silicon layer, where the sequential etching is undertaken employing in situ in a single plasma reactor chamber or cluster of adjoining chambers a sequential plasma etch method employing a sequence of etching gas compositions which upon plasma activation perform the etching reactions with uniform linewidth dimensions and attenuated polymer residue formation and defect levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.