Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region

US6686624B2 · kind B2 · utility

Assignee

• Monolithic System Technology, Inc. · US

Inventor

• Fu-Chieh Hsu · Saratoga, US

Key dates

• Filing date: Mar 11, 2002
• Grant date: Feb 3, 2004
• Expiry date: Mar 11, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/488

Abstract

A vertical one-transistor, floating-body DRAM cell is fabricated by forming an isolation region in a semiconductor substrate, thereby defining a semiconductor island in the substrate. A buried source region is formed in the substrate, wherein the top/bottom interfaces of the buried source region are located above/below the bottom of the isolation region, respectively. A recessed region is etched into the isolation region, thereby exposing sidewalls of the semiconductor island, which extend below the top interface of the buried source region. A gate dielectric is formed over the exposed sidewalls, and a gate electrode is formed in the recessed region, over the gate dielectric. A drain region is formed at the upper surface of the semiconductor island region, thereby forming a floating body region between the drain region and the buried source region. Dielectric spacers are formed adjacent to the gate electrode, thereby covering exposed edges of the gate dielectric.