Damascene double-gate MOSFET structure and its fabrication method
US6686630B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2001 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Feb 7, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/027
Abstract
The present invention provides a method for fabricating sub-0.05 &mgr;m double-gated MOSFET devices utilizing a damascene-gate process. The damascene-gate process provides sub-0.05 &mgr;m double-gated MOSFET devices which include a frontside poly gate electrode and a backside implant region. The two gates are separated by two gate dielectrics that include a thin (on the order of about 200 å or less) Si layer which is sandwiched between the gate dielectrics. The Si layer serves as the channel region of the device. Short-channel effects are greatly suppressed in the present double-gate MOSFET device because the two gates terminate the drain filed lines, preventing the drain potential from being felt at the source end of the channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.