Multiple chip stack structure and cooling system
US6686654B2 · kind B2 · utility
85Cited by
43References
41Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2001 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Aug 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic package comprised of multiple chip stacks attached together to form a single, compact electronic module. The module is hermetically sealed in an enclosure. The enclosure comprises a pressurized, thermally conductive fluid, which is utilized for cooling the enclosed chip stack. A structure that allows for densely-packed, multiple chip stack electronic packages to be manufactured with improved heat dissipation efficiency, thus improving the performance and reliability of the multi-chip electronic packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.