Integrated multi-chip chip scale package
US6686656B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2003 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Jan 13, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertically integrated chip scale package (CSP) assembly comprising two or more single chip package subassemblies having an upper level CSP subassembly superimposed directly above a lower level CSP subassembly. The lower-most CSP subassembly in the vertical stack contains an array of solder balls for interconnection to a printed wiring board. The vertical electrical connection between the upper and lower level package subassemblies is accomplished by using wire bonding from perimeter wire bonding pads located on an upper level substrate extension to matching perimeter wire bonding pads located on a lower level substrate extension that is longer in length than the upper level substrate extension. The stacked package subassemblies are bonded together by using a thin adhesive material, and the perimeter wire bonds are encapsulated by an encapsulant for protection. The assembled vertical stack has the appearance of a single CSP but is shorter in height than two individual packages that are stacked together with solder ball interconnects located therebetween.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.