Apparatus and method for reducing reflexions in a memory bus system
US6686764B2 · kind B2 · utility
1Cited by
3References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 14, 2002 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Jun 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4086
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to an apparatus and a method for reducing reflexions in a bus for transmitting data. The device comprises an output, which is connected to an input of the bus, a device for sending a test signal into the input of the bus (102), the device for sending being connected to the output, a device for receiving reflexions from the bus, which is connected to the output, and a device for evaluating the reflexions from the bus, in order to supply an evaluation result, and for setting an impedance at the output as a function of the evaluation result, in order to reduce the reflexions from the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.