Delay circuit of clock synchronization device using delay cells having wide delay range
US6686788B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2002 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | May 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit of a clock synchronization device that includes an operational amplifier for setting the level of a current control voltage according to a voltage difference between a regulation voltage and a reference voltage. A number of unit delay cells connected in series are included, each having a delay time set according to a resistance control voltage and the current control voltage. Also, a variable resistance unit is included having a resistance value adjusted according to the resistance control voltage, where the variable resistance unit includes a cross coupled adjustment device that outputs signals to a next unit delay cell. The delay cells are controlled by using the operational amplifier and a replica cell to have a wide delay range. As a result, the working range can be set wide, jitters may be reduced and the chip size may also be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.