Optimizing the translation of virtual addresses into physical addresses using a pipeline implementation for least recently used pointer
US6686920B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2000 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | May 10, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method are provided for optimizing the translation of virtual addresses into physical addresses for a graphics address remapping table (GART). In the system and method, a translation look-aside buffer cache has a plurality of translation look-aside buffer entries. Each translation look-aside buffer entry is operable to buffer information which may be accessed for use in translating a virtual address into a physical address. A least recently used pointer circuit is operable to point to a translation look-aside buffer entry buffering information least recently used in the translation look-aside buffer cache. During operation, updates to the least recently used pointer circuit may be pipelined with corresponding accesses to the translation look-aside buffer cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.