Reference voltage generation for memory circuits
US6687150B1 · kind B1 · utility
8Cited by
2References
27Claims
0Family size
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Key dates
| Filing date | Sep 4, 2002 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Sep 4, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved reference voltage generation is described. In one embodiment, a memory block includes a plurality of memory cells interconnected by wordlines and bitlines. A plurality of reference cells are provided. A bitline includes a reference cell. The bitlines of the memory block are divided into groups or bitlines. The reference cells within a group are interconnected to average out the reference cell charge variation to improve the sensing window.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.