Dual reference cell for split-gate nonvolatile semiconductor memory
US6687162B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2002 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Apr 19, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques to more accurately read values stored in data cells. In an aspect, one reference cell is provided for each group of data cells having similar configuration (e.g., similar layout and orientation). For split-gate memory cells arranged in pairs, each pair includes two data cells implemented as mirrored image of one another. Two reference cells may then be used, one reference cell for each data cell in a pair. In another aspect, the data paths for the reference and data cells for read operation are matched. This matching may be achieved by using the same circuit design for the data and reference sense amplifiers, using the same layout and orientation for the sense amplifiers, matching the lines for the two data paths, matching the structure (e.g., length and width) and the diffusion region (e.g., doping concentration and contact) for the sense amplifiers and lines, and so on.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.