Data processing system and method of communication that reduce latency of write transactions subject to retry
US6687795B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2000 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Aug 1, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a plurality of snoopers coupled to an interconnect. In response to a memory access request transmitted on an interconnect by one of the snoopers receiving a Retry response, a determination is made whether or not the Retry response was caused by a target snooper that will service the memory access request. If not, the target snooper services the memory access request in spite of the Retry response. In a preferred embodiment in which the memory access request is a write request and the target snooper is a memory controller, stale data cached by at least one snooper in association with the address are also invalidated by a snooper, such as the memory controller, transmitting at least one address-only kill transaction on the interconnect. Advantageously, the address-only kill transaction can be issued concurrently with or following servicing the write request so that the write request does not incur latency by waiting until all stale copies of the data have been invalidated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.