Method for optimizing loop bandwidth in delay locked loops
US6687881B2 · kind B2 · utility
12Cited by
7References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2002 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Feb 14, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for optimizing loop bandwidth in a delay locked loop is provided. A representative power supply waveform having noise is input into a simulation of the delay locked loop; an estimate of jitter is determined; and the loop bandwidth of the delay looked loop is adjusted until the jitter falls below a pre-selected value. Further, a computer system for optimizing loop bandwidth in a delay locked loop is provided. Further, a computer-readable medium having recorded thereon instructions adapted to optimize loop bandwidth in a delay locked loop is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.