System and method for inserting leakage reduction control in logic circuits
US6687883B2 · kind B2 · utility
25Cited by
7References
46Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2000 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Apr 18, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing leakage power of a logic network comprising the steps of: using (observability) don't care information to identify “sleep states” for individual nets; determining based on probabilistic analysis at least one net in which expected power consumption will be reduced by forcing a net to a particular value during at least a portion of a “sleep state”; and forcing the determined net to the determined value determined portion of that “sleep state”.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.