Process for manufacturing micromechanical components in a semiconductor material wafer with reduction in the starting wafer thickness
US6689627B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2001 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | Jan 21, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76256
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for manufacturing components in a multi-layer wafer, including the steps of: providing a multi-layer wafer comprising a first semiconductor material layer, a second semiconductor material layer (, and a dielectric material layer arranged between the first and the second semiconductor material layer; and removing the first semiconductor material layer initially by mechanically thinning the first semiconductor material layer, so as to form a residual conductive layer, and subsequently by chemically removing the residual conductive layer. In one application, the multi-layer wafer is bonded to a first wafer of semiconductor material, with the second semiconductor material layer facing the first wafer, after micro-electromechanical structures have been formed in the second semiconductor material layer of the multi-layer wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.