Method for production process for the local interconnection level using a dielectric conducting pair on pair
US6689655B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2002 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | Jun 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76841
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.