Philippe Coronel
98Patents
15h-index
87Co-inventors
87Inventor score
Filing activity: Sep 29, 1995 → Nov 22, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6363294B1 | Method and system for semiconductor wafer fabrication process real-time in-situ interactive supervision | Electricity | 402 | Expired |
| US7687872B2 | Back-lit image sensor with a uniform substrate temperature | Electricity | 181 | Active |
| US8039332B2 | Method of manufacturing a buried-gate semiconductor device and corresponding integrated circuit | Electricity | 124 | Active |
| US7910419B2 | SOI transistor with self-aligned ground plane and gate and buried oxide of variable thickness | Electricity | 107 | Active |
| US5658418A | Apparatus for monitoring the dry etching of a dielectric film to a given thickness in an integrated circuit | Electricity | 98 | Expired |
| US6828646B2 | Isolating trench and manufacturing process | Electricity | 70 | Expired |
| US8669171B2 | Method for eliminating the metal catalyst residues on the surface of wires produced by catalytic growth | Electricity | 58 | Active |
| US8186568B2 | Assembly of two parts of an integrated electronic circuit | Emerging Cross-Sectional Technologies | 52 | Active |
| US5807761A | Method for real-time in-situ monitoring of a trench formation process | Electricity | 50 | Expired |
| US6969878B2 | Surround-gate semiconductor device encapsulated in an insulating medium | Electricity | 43 | Expired |
| US6342452B1 | Method of fabricating a Si3N4/polycide structure using a dielectric sacrificial layer as a mask | Electricity | 31 | Expired |
| US7923315B2 | Manufacturing method for planar independent-gate or gate-all-around transistors | Electricity | 28 | Active |
| US5874345A | Method for planarizing TEOS SiO.sub.2 filled shallow isolation trenches | Emerging Cross-Sectional Technologies | 19 | Expired |
| US6846690B2 | Integrated circuit comprising an auxiliary component, for example a passive component or a microelectromechanical system, placed above an electronic chip, and the corresponding fabrication process | Performing Operations; Transporting | 16 | Expired |
| US6281068A | Method for buried plate formation in deep trench capacitors | Electricity | 15 | Expired |
| US7804134B2 | MOSFET on SOI device | Electricity | 14 | Active |
| US6417072B2 | Method of forming STI oxide regions and alignment marks in a semiconductor structure with one masking step | Electricity | 11 | Expired |
| US7687356B2 | Formation of shallow siGe conduction channel | Electricity | 10 | Active |
| US8460978B2 | Method for manufacturing a transistor with parallel semiconductor nanofingers | Electricity | 9 | Active |
| US6689655B2 | Method for production process for the local interconnection level using a dielectric conducting pair on pair | Electricity | 9 | Expired |
| US6297089A | Method of forming buried straps in DRAMs | Electricity | 8 | Expired |
| US7556995B2 | MOS transistor manufacturing | Electricity | 7 | Active |
| US7687833B2 | Component containing a baw filter | Electricity | 7 | Active |
| US8203182B2 | FinFET with two independent gates and method for fabricating the same | Electricity | 6 | Active |
| US7141837B2 | High-density MOS transistor | Electricity | 6 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.