Method of forming an STI feature while avoiding or reducing divot formation
US6689665B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2002 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | Oct 11, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/95
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming shallow trench isolation (STI) features to reduce or avoid divot formation at STI trench corners including providing a shallow trench isolation (STI) feature included in a semiconductor process surface the STI feature including an anisotropically etched trench formed into a semiconductor substrate extending through a thickness including a thermally grown silicon dioxide layer overlying the semiconductor substrate and a metal nitride hardmask layer overlying the thermally grown silicon dioxide layer said anisotropically etched trench being back filled with a silicon dioxide filling material; removing excess silicon dioxide filling material overlying the hardmask layer according to a chemical mechanical polishing (CMP) process; removing the hard mask layer according to a wet chemical etching process; and, re-growing the thermally grown silicon dioxide layer including re-oxidizing to at least an originally formed thermally grown silicon dioxide layer thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.