Minimization and linearization of ESD parasitic capacitance in integrated circuits

US6690066B1 · kind B1 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Heng-Chih Lin · Hsinchu, TW
• Charvaka Duvvury · Plano, US
• Baher Haroun · Allen, US

Key dates

• Filing date: Oct 18, 2002
• Grant date: Feb 10, 2004
• Expiry date: Oct 18, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/811

Abstract

An integrated circuit protecting an I/O pad 303 against an ESD pulse, the circuit having in the same substrate a discharge sub-circuit 301 and a drive sub-circuit 302, each sub-circuit including an MOS transistor. The circuit comprises a direct connection between the I/O pad 303 and the drain 321 of the drive sub-circuit MOS transistor 306, and further a forward diode 360 inserted between the I/O pad 303 and the drain 311 of the discharge sub-circuit MOS transistor 305 to isolate the junction capacitance of the discharge sub-circuit MOS transistor, whereby electrical noise coupling to the substrate is reduced, RF/analog input signals are improved, and leakage at the I/O pad is reduced.