Semiconductor integrated circuit device
US6690206B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2002 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | Apr 5, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pass-transistor logic circuit configuration that can form a high-speed chip in a small area with short wire length. In a selector circuit PMOS and NMOS transistors with different gate signals but with the same drain outputs are arranged, respectively, so their diffusion layers are shared. The PMOS and NMOS are staggered so that their gates are almost in line. With this arrangement, wires connecting drains of the PMOS and NMOS and wires connecting sources of the PMOS and NMOS do not intersect each other, so they can be wired with only the first wiring layer. Further, gate input signals can be wired with only polysilicon wires without crossing each other. The pass-transistor logic circuit is made to pass through the signal buffers before or after it is connected to the selector. This can make a compact, fast circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.