Register files and caches with digital sub-threshold leakage current calibration
US6690604B2 · kind B2 · utility
19Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2001 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | Jun 3, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit, such as a cache or register file, where the keeper functional units are digitally controlled to compensate for variable sub-threshold leakage current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.