Patent · US Expired

Logic signal level converter circuit and memory data output buffer using the same

US6690605B2 · kind B2 · utility

4Cited by

5References

9Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Andre Schäfer · Hersbruck, DE
Joachim Schnabel · Hersbruck, DE

Key dates

Filing date	Apr 9, 2003
Grant date	Feb 10, 2004
Priority date	—
Expiry date	Apr 9, 2023

Classification

Technology area (CPC H)Electricity
CPC primaryH03K3/356113
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A circuit configuration for converting logic signal levels has two level converters, to which an input signal to be converted is fed complementarily. The level converters generate a rising or falling edge with a different gradient. The output signals of the level converters are combined in a logic combination element. The logic combination element drives a togglable storage element, which provides the level-converted output signal. The duty ratio of the input signal is not changed during the level conversion, independently of production-dictated variations in the component parameters.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.