Loading previously dispatched slots in multiple instruction dispatch buffer before dispatching remaining slots for parallel execution
US6691221B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 24, 2001 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | May 24, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the first instruction storing circuit dispatches L instructions stored in the first instruction storing circuit, wherein L is less than or equal to N. An instruction loading circuit, coupled to the instruction dispatch circuit and to the first and second instruction storing circuits, loads L instructions from the second instruction storing circuit into the first instruction storing circuit after the L instructions are dispatched from the first instruction storing circuit and before further instructions are dispatched from the first instruction storing circuit. The instruction loading circuit loads the L instructions from the second instruction storing circuit into the positions previously occupied by the L instructions dispatched from the first instruction storing circuit. A feedback path is also provided to reload an instruction not previously dispatched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.