Flip-chip bumbing method for fabricating solder bumps on semiconductor wafer
US6692629B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2000 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | Apr 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A flip-chip bumping method is proposed for the fabrication of solder bumps on a semiconductor wafer for flip-chip application. The proposed flip-chip bumping method is intended for use on a semiconductor wafer predefined with a plurality of chip regions which are delimited from each other by a predefined cutting line and each of which is formed with a plurality of aluminum or copper based bond pads, and is characterized in the provision of a plating bus over and along the cutting line and connected to each bond pad. By means of this plating bus, the required UBM (Under Bump Metallization) fabrication and solder-bump fabrication can be both carried out through plating. Since plating process is considerably lower in cost than sputtering process and etching process, the proposed flip-chip bumping method can be more cost-effective to implement than prior art.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.