Process for forming a buried cavity in a semiconductor material wafer and a buried cavity
US6693039B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2001 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | May 19, 2021 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C1/00404
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The process comprises the steps of forming, on top of a semiconductor material wafer, a holed mask having a lattice structure and comprising a plurality of openings each having a substantially square shape and a side with an inclination of 45° with respect to the flat of the wafer; carrying out an anisotropic etch in TMAH of the wafer, using said holed mask, thus forming a cavity, the cross section of which has the shape of an upside-down isosceles trapezium; and carrying out a chemical vapor deposition using TEOS, thus forming a TEOS layer which completely closes the openings of the holed mask and defines a diaphragm overlying the cavity and on which a suspended integrated structure can subsequently be manufactured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.