Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity
US6693357B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2003 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | Mar 13, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices and manufacturing methods therefor are disclosed, in which conductive fill structures are provided in fill regions in an interconnect wiring layer between conductive wiring structures to facilitate planarization uniformity during metalization processing. One approach employs fill structures of varying sizes where smaller fill structures are formed near wiring regions having high aspect ratio wiring structures and larger fill structures are located near wiring regions with lower aspect ratio wiring structures. Another approach provides fill structures with varying amounts of openings, with fill structures having few or no openings being provided near low aspect ratio wiring structures and fill structures having more openings being located near higher aspect ratio wiring structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.