Packaging of integrated circuits and vertical integration
US6693361B1 · kind B1 · utility
328Cited by
36References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2000 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | Nov 16, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/12507
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first level packaging wafer is made of a semiconductor or insulating material. The bumps on the wafer are made using vertical integration technology, without solder or electroplating. More particularly, vias are etched part way into a first surface of the substrate. Metal is deposited into the vias. Then the substrate is blanket-etched from the back side until the metal is exposed and protrudes from the vias to form suitable bumps. Dicing methods and vertical integration methods are also provided. Solder or electroplating are used in some embodiments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.