Sergey Savastiouk
28Patents
15h-index
12Co-inventors
74Inventor score
Filing activity: Dec 6, 1999 → Aug 12, 2015
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6322903A | Package of integrated circuits and vertical integration | Emerging Cross-Sectional Technologies | 743 | Expired |
| US7049170B2 | Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities | Electricity | 352 | Expired |
| US6693361B1 | Packaging of integrated circuits and vertical integration | Emerging Cross-Sectional Technologies | 328 | Expired |
| US7060601B2 | Packaging substrates for integrated circuits and soldering methods | Electricity | 326 | Expired |
| US6897148B2 | Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby | Emerging Cross-Sectional Technologies | 86 | Expired |
| US7034401B2 | Packaging substrates for integrated circuits and soldering methods | Electricity | 83 | Expired |
| US7241641B2 | Attachment of integrated circuit structures and other substrates to substrates with vias | Electricity | 56 | Expired |
| US6498074B2 | Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners | Emerging Cross-Sectional Technologies | 53 | Expired |
| US7186586B2 | Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities | Electricity | 49 | Expired |
| US7241675B2 | Attachment of integrated circuit structures and other substrates to substrates with vias | Electricity | 46 | Expired |
| US7521360B2 | Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby | Emerging Cross-Sectional Technologies | 37 | Active |
| US7510928B2 | Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques | Electricity | 30 | Expired |
| US6402843B1 | Non-contact workpiece holder | Electricity | 30 | Expired |
| US6448153B2 | Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners | Electricity | 17 | Expired |
| US7964508B2 | Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques | Electricity | 16 | Active |
| US6203661A | Brim and gas escape for non-contact wafer holder | Electricity | 12 | Expired |
| US9018094B2 | Substrates with through vias with conductive features for connection to integrated circuit elements, and methods for forming through vias in substrates | Electricity | 10 | Active |
| US9111902B2 | Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques | Electricity | 7 | Active |
| US8757897B2 | Optical interposer | Physics | 4 | Active |
| US6667242B2 | Brim and gas escape for non-contact wafer holder | Electricity | 3 | Expired |
| US9323010B2 | Structures formed using monocrystalline silicon and/or other materials for optical and other applications | Emerging Cross-Sectional Technologies | 3 | Active |
| US8431431B2 | Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers | Electricity | 2 | Active |
| US9589879B2 | Substrates with through vias with conductive features for connection to integrated circuit elements, and methods for forming through vias in substrates | Electricity | 1 | Active |
| US8829683B2 | Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers | Electricity | 1 | Active |
| US8633589B2 | Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.