System for the design of high-performance communication architecture for system-on-chips using communication architecture tuners
US6694488B1 · kind B1 · utility
4Cited by
2References
10Claims
0Family size
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Key dates
| Filing date | May 24, 2000 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | May 24, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic system with a plurality of components interconnected by a plurality of shared communication channels. At least one component comprises a communication architecture tuner. The tuner enables the electronic system to adapt to changing communication needs of the electronic system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.