Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing
US6696332B2 · kind B2 · utility
82Cited by
3References
12Claims
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Key dates
| Filing date | Jun 21, 2002 |
| Grant date | Feb 24, 2004 |
| Priority date | — |
| Expiry date | Jun 21, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/033
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods are disclosed for forming gate dielectrics for MOSFET transistors, wherein a bilayer deposition of a nitride layer and an oxide layer are used to form a gate dielectric stack. The nitride layer is formed on the substrate to prevent oxidation of the substrate material during deposition of the oxide layer, thereby avoiding or mitigating formation of low-k interfacial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.