Structure and method for a junction field effect transistor with reduced gate capacitance
US6696706B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 22, 2002 |
| Grant date | Feb 24, 2004 |
| Priority date | — |
| Expiry date | Oct 22, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/914
Abstract
An apparatus and method for a semiconductor device with reduced gate capacitance. Specifically, an n-channel or p-channel junction field effect transistor (JFET) is described comprising an appropriately doped substrate forming a drain region, an epitaxial layer formed on top of the substrate, a control structure comprising a gate region implanted into the epitaxial layer, a source region sharing a p-n junction with the gate region, and an altered epitaxial region. The altered epitaxial region is formed by implanting either n− or p− dopants directly below the gate region of either the n-channel or p-channel JFET for widening a depletion region surrounding the gate region. The enlarged depletion region reduces the gate capacitance of the JFET between the gate and drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.