Solder ball allocation on a chip and method of the same
US6696763B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2001 |
| Grant date | Feb 24, 2004 |
| Priority date | — |
| Expiry date | Feb 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A solder ball allocation on a chip, and a method of the same are provided. The chip has a substrate, first solder balls and second solder balls. The first solder balls are located on a periphery of the substrate and arranged outwardly. The second solder balls are located in a central part of the substrate and arranged with several first geometric patterns that construct a second geometric pattern. The first geometric patterns are also arranged to divide the chip into several power source blocks. The conflict between the second solder balls and the power source blocks are analyzed to remove the second solder balls with conflicts. The power line can go through the middle directly to avoid the power source bypass, or other reasons that cause the chip unable to work stable. The invention divides the chip into several power source blocks without increase the chip volume and cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.