Methods of fabricating ferroelectric memory devices having a ferroelectric planarization layer
US6699725B2 · kind B2 · utility
39Cited by
2References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 5, 2002 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | Jun 5, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the present invention, ferroelectric memory devices using a ferroelectric planarization layer and methods of fabricating the same are disclosed. According to the method of the present invention, a conductive layer is formed on an interlayer insulation layer having a contact plug and patterned to form capacitor bottom electrode patterns. A ferroelectric layer for planarization is formed to fill a space between the bottom electrode patterns, and then another ferroelectric layer for a capacitor is formed on the bottom electrode pattern and the ferroelectric layer for planarization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.