Method of fabricating a wafer level package
US6699782B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 2001 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | Apr 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabrication method of wafer level packages capable of improving reliability by maximizing a contact area of metal wiring and a conductive ball and of simplifying fabrication processes by reducing the number of sputtering. The disclosed method comprises the steps of: providing a substrate having a plurality of chip pads on the upper part thereof; forming a first insulating layer including a first opening exposing the chip pad and a second opening forming a ball land on the substrate; forming metal wiring connected to the chip pad in a single unit through the first opening and covering the second opening to have a ball land on the first insulating layer; forming a second insulating layer including a third opening which covers the metal wiring, however, exposes the ball land; and adhering a conductive ball to be in contact with the third opening on the ball land.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.