Vertical semiconductor device having alternating conductivity semiconductor regions
US6700175B1 · kind B1 · utility
47Cited by
14References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2001 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | Dec 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is provided a method of manufacturing a vertical semiconductor device including a structural section in which an n−-type semiconductor region and a p−-type semiconductor region are arranged alternately without filling trenches by epitaxial growth. A p−-type silicon layer (13) which becomes a p−-type semiconductor region (12) is formed. An n−-type semiconductor region (11) is formed by diffusing n-type impurities into the p−-type silicon layer (13) through the sidewalls of first trenches (22) formed in the p−-type silicon layer (13).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.