Partial underfill for flip-chip electronic packages
US6700209B1 · kind B1 · utility
16Cited by
25References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1999 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | Nov 25, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package that contains an underfill material between an integrated circuit and a substrate. The integrated circuit may be mounted to the substrate with solder bumps in a C4 process. The underfill material may extend from an edge of the integrated circuit a length that is no less than approximately 25% of the length between the integrated circuit edge and the integrated circuit center. It has been discovered that a length greater than approximately 25% does not provide a significant reduction in the strain of the solder bumps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.