Adjustment and calibration system to store resistance settings to control chip/package resonance
US6700390B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2002 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | May 31, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/189
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A adjustment and calibration system for reducing an impedance of a power supply path of an integrated circuit is provided. The power supply path includes a first power supply line and a second power supply line to provide power to the integrated circuit. At least a digital potentiometer connected between the first power supply line and the second power supply line is adjusted to reduce the impedance of the power supply path. Control information, representative of a desired value for the digital potentiometer, is stored in a storage device. The control information stored in the storage device is subsequently selectively read out in order to adjust the digital potentiometer to a state corresponding to the control information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.