Sense amplifier bias circuit for a memory having at least two distinct resistance states
US6700814B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2002 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | Dec 14, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory, a bias circuit (112, 212, 312, 412) uses a current reference (108) for providing a reference current and control circuitry (106, 120) to bias a sense amplifier (114) with a varying voltage (VB). The varying voltage maintains current through MRAM bit cells (177-179) at a value proportional to the reference current over variations in average bit cell resistance with immunity to variations in process, supply voltage and temperature. In one form, a mock sense amplifier (122, 126, 132, 134) and mock array of bit cells (130, 136) are used to establish internal steady state voltages equivalent to a steady state condition of the sense amplifier with equalized outputs and to generate the varying bias voltage. Matching diode-connected transistors in each of the control circuitry and either the mock sense amplifier or the sense amplifier is used to generate the varying bias voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.