Aggressive capacitor array cell layout for narrow diameter DRAM trench capacitor structures via SOI technology
US6703273B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2002 |
| Grant date | Mar 9, 2004 |
| Priority date | — |
| Expiry date | May 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0387
Abstract
A method of increasing DRAM cell capacitance via formation of deep, wide diameter trench capacitor structures, has been developed. An underlying semiconductor substrate is used to accommodate deep, wide diameter trench capacitor structures while an overlying, bonded, thinned semiconductor substrate is used to accommodate narrow diameter trench structures, in turn used for communication to the underlying deep trench capacitor structures, as well as to accommodate the elements of the DRAM device, such as the transfer gate transistors. The use of an underlying semiconductor substrate for accommodation of the trench capacitor structures allows a wider diameter structures to be used, thus reducing patterning difficulties encountered when forming narrow diameter, deep trench capacitor structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.