Stackable memory module with variable bandwidth
US6705877B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2003 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Jan 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01R12/716
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present invention is a family of memory modules. In one embodiment a memory module with granularity and upgradeability of bandwidth, and a low profile uses 256 MB SDRAM or DDR SDRAM memory devices in chip scale packages (CSPs) to support a memory data bus width of up to at least 512 bits. Each module includes an impedance-controlled substrate having contact pads, memory devices, and other components on its surfaces. In one embodiment, the inclusion of spaced apart multiple area array interconnections allows a row of memory devices to be symmetrically mounted on each side of each of the area array interconnections, thereby reducing the interconnect lengths and facilitating matching of interconnect lengths. Short area array interconnections, including ball grid array (BGA) and land grid array (LGA) options, provide electrical communication between modules and the rest of the system. Thermal control structures may be included to maintain reliable operating temperatures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.