Application of InAIAs double-layer to block dopant out-diffusion in III-V device Fabrication
US6706542B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2000 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Mar 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/8242
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present invention relates to a multi-layer dopant barrier and its method of fabrication for use in semiconductor structures. In an illustrative embodiment, the multi-layer dopant barrier is disposed between a first doped layer and a second doped layer. The multi-layer dopant barrier further includes a first dopant blocking layer adjacent the first doped layer and a second dopant blocking layer adjacent the second doped layer. A technique for fabricating the multi layer dopant barrier is disclosed. A first dopant blocking layer is formed at a first temperature, and a second dopant blocking layer is formed at a second temperature over the first barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.