Method of forming an alignment feature in or on a multi-layered semiconductor structure
US6706609B2 · kind B2 · utility
2Cited by
16References
19Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | May 29, 2001 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | May 29, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/975
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.