Methods for manufacturing stacked gates including oxide/nitride/oxide (ONO) interlayer dielectrics using pre-annealing and/or post-annealing in nitrogen
US6706613B2 · kind B2 · utility
4Cited by
3References
29Claims
0Family size
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Key dates
| Filing date | Feb 6, 2003 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Feb 6, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A semiconductor device including a stacked gate having stacked gate sidewalls and an oxide/nitride/oxide (ONO) interlayer dielectric is manufactured by pre-annealing the stacked gate in a first atmosphere that includes nitrogen. At least a portion of the stacked gate sidewalls of the stacked gate that has been pre-annealed is oxidized. Post-annealing is then performed on the stacked gate including the stacked gate sidewalls that have been oxidized, in a second atmosphere that includes nitrogen.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.