Innovative method to build a high precision analog capacitor with low voltage coefficient and hysteresis
US6706635B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2002 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Jul 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76838
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method for forming an anlog capacitor on a semiconductor substrate. The method comprises forming a field oxide over a portion of the substrate, and forming a polysilicon layer over the field oxide layer, and subsequently forming a silicide over the polysilicon layer. A first interlayer dielectric layer is formed over the substrate, and a capacitor masking pattern is formed. The first interlayer dielectric is etched using the capacitor masking pattern as a mask and the silicide layer as an etch stop, and a thin dielectric is formed over the substrate. A contact masking pattern is formed over the substrate, and a subsequent etch is performed on the thin dielectric and the first interlayer dielectric using the silicide and substrate as an etch stop. A metal layer is deposited over the substrate, and is subsequently planarized, thereby defining an analog capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.